Each new generation of semiconductor technology demands higher performance in semiconductor devices, particularly in the performance of CMOS transistors. One of the key metrics of transistor performance is the on-current of the transistor per unit width, typically measured in hundreds of microamperes per micron of the channel width, or “gate width” as it is commonly referred to. Various methods have been considered and practiced to enhance the on-current of the CMOS transistors, that is, both PFETs (transistors wherein the minority carriers are holes, which are p-type carriers), and NFETs (transistors wherein the minority carriers are electrons, which are n-type carriers). Among them, improving the mobility of minority carriers in the channel is the most common method of enhancing the on-current of the CMOS transistors. Some of these methods utilize inherent differences in the mobility of carriers along the different crystallographic orientations of the semiconductor crystal, while some others utilize the changes in the mobility of the carriers under stress in the plane of the channel.
In the case of the latter, wherein stress within the channel of a CMOS transistor is altered, a few different approaches exist. According to a first approach, the semiconductor lattice is implanted with atoms with similar electronic properties but with different lattice constants. All of silicon, germanium, and carbon have identical electronic outer shells and the same crystal structure, namely, “the diamond structure,” with their room temperature lattice constants of 0.5431 nm, 0.565 nm, and 0.357 nm, respectively. Substitution of some of the atoms in a crystal that are made up of one type of atoms with atoms of different species fabricates a crystal with an altered natural lattice constant from that of the original crystal. Natural lattice constant herein denotes the lattice constant of the material when no stress is applied externally. For the purposes of silicon based semiconductor devices, silicon crystals with a small percentage of carbon or germanium in substitutional sites are commonly used. When substitutional alloys of such materials are epitaxially disposed on a silicon substrate, stress is applied to the material since the alloy is now forced to have the same lattice constant as the underlying silicon instead of its own natural lattice constant. However, as demonstrated in FIG. 9 in Ernst et al., “Fabrication of a novel strained SiGe:C-channel planar 55 nm n-MOSFET for High-Performance CMOS,” VLSI Symp., 2002, pp. 92-93, the substitutional atoms in the alloy serve as scattering centers and actually degrade the mobility. Similar problems are encountered with substitutional alloys of silicon and germanium.
A second approach is to build the channel of a CMOS transistor on a silicon layer that is epitaxially deposited on a crystalline silicon alloy with an altered lattice constant different from that of silicon. Specifically, the silicon layer is constructed essentially with silicon, having a low level of electrical doping as necessary but does not contain a silicon carbon alloy or a silicon germanium alloy to avoid the problems of the first approach. However, the substrate itself has an altered lattice constant. For example, a smaller lattice constant compared with that of silicon is achieved by alloying silicon with a small percentage of carbon, e.g., between 0% and 10% in atomic concentration. In this alloy, the carbon atoms are placed substitutionally, that is, replacing the silicon atoms from the structure of the crystal, as opposed to interstitially, that is, by being placed between the sites that the original silicon atoms are still occupying. In another example, a larger lattice constant compared with that of silicon is achieved by alloying silicon with germanium, e.g. between 0% and 40% in atomic concentration. In the process of manufacturing these devices, a substrate with an altered lattice constant is formed first, followed by the formation of a strained silicon layer through epitaxial deposition of silicon. Cheng et al., “Electron Mobility Enhancement in Strained-Si n-MOSFETs Fabricated on SiGe-on Insulator (SGOI) Substrates,” IEEE Electron Device Letters, Vol. 22, No. 7, July 2001 demonstrates an example of such an approach with improvement in the performance of PFETs.
While the second approach does produce devices with improved performance, such an approach faces some challenges in that the formation of a crystalline structure with an altered lattice parameter generally depends on the structural relaxation of the epitaxially grown alloy material, be it an alloy of silicon and germanium or an alloy of silicon and carbon, through the generation of misfit dislocations, which are crystalline defects in thick films. When the film is thin, the epitaxial alignment of the alloy to the underlying silicon substrate is preserved, therefore keeping the lattice constant in the plane of the epitaxial growth exactly the same as the underlying silicon substrate. Only when the alloy becomes thicker does the alloy relax and its lattice constant approaches the natural value for the alloy. Typically, the thickness required for full relaxation and reduction of the crystalline defects in the alloy to an acceptable level is on the order of 1,000 nm. Methods of improving the film quality is also known in the prior art.
As far as the performance of the CMOS transistors built with silicon channels are concerned, NFETs and PFETs require the opposite kind of stress. Specifically, the hole mobility is enhanced in a PFET when a compressive stress is applied to the channel along the direction of the movement of the holes, that is, in the direction of a line connecting the source and the drain. However, the electron mobility is enhanced in an NPFET when a tensile stress is applied to the channel along the direction of the movement of the electrons. Manufacturing both PFETs and NFETs with enhanced mobility through stress engineering on the same substrate, therefore, creates a challenge in that two types of substrate areas with an altered lattice parameter need to be fabricated. Such methods have been disclosed in the prior art, for example, in the U.S. patent application Publication No. US2005/0104131 A1 and in the U.S. patent application Publication No. US2005/0130358 A1. However, the general complexity of such processes still remains a challenge.
A third type of approach produces stress in the channel region by embedding an epitaxial alloy of silicon and carbon or, of silicon and germanium, within the source and the drain region of a transistor. Hence, they are called embedded epitaxial alloys. The most common choice of material includes an epitaxial silicon germanium alloy and epitaxial silicon carbon alloy (Si:C) on silicon substrates. According to this approach, the vertical dimensions of the alloy material in the source and the drain are much less than what is required for the alloy to generate misfit locations and relax. So the alloy material within the source and the drain maintains epitaxial alignment with the underlying silicon substrate. The lattice constant in the plane of the epitaxial alignment, which is the same as the plane in which the channel is located, remains identical to the lattice constant of the underlying silicon substrate. Since the alloy in the source and the drain has a different lattice constant than the natural lattice constant of the alloy, stress is exerted on the alloy itself and the alloy in turn exerts stress on the surrounding structures. The channel of the transistor located between a source and the drain is consequently stressed.
As noted above, the desired type of stress is different between NFET channels and PFET channels. For PFETs, the desired stress is a compressive stress along the direction of the line connecting the source and the drain. An epitaxial alloy of silicon and germanium in the source and the drain exerts such uniaxial stress on the channel. Ghani et al., “A 90 nm high Volume manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors,” Proc. IEDM, pp. 978-980, 2003 reported a successful implementation of this technology for the improvement of PFET performance. Likewise, NFETs require a tensile stress along the direction of the line connecting the source and the drain. An epitaxial alloy of silicon and carbon in the source and drain exerts such stress on the channel. Ang et al., “Thin Body Silicon-on-insulator N-MOSFET with Silicon-Carbon Source and drain regions for Performance Enhancement,” IEEE International Electron Device Meeting 2005, December 2005, pp. 503-506 reported improved NFET performance through the use of this technology.
As in the case of the second approach discussed above, a successful implementation of both PFETs and NFETs with enhanced mobility through stress engineering on the same silicon substrate requires a complex integration of processing steps. The U.S. patent application Publication No. US 2005/0082616 A1 discloses methods and structures of implementing particular versions of the PFETs and NFETs with enhanced mobility through stress engineering. In summary, for each type of CMOS transistors, the source and the drain regions of the transistors are etched and silicon alloys are epitaxially grown within the etched region. The masking of one type of transistors and etching of the other type of transistors are performed sequentially. Also, the silicon alloy material for each type of transistors is selected appropriately so that the stress exerted on the channel of the transistors enhances the mobility of the minority carriers in the channel.
During the research leading to the present invention, some problems in the manufacturing of enhanced mobility transistors as disclosed in Cheng et al., have been discovered. The first problem is a degradation of contact resistance on SiGe alloy. As the content of germanium increases, the contact resistance to the source and drain also tends to increase and degrade the performance of PFETs with embedded SiGe alloy in the source and the drain. This is because the alloy of metal silicide and metal germanide, which is formed by depositing a metal on the source and drain containing silicon and germanium and annealing the structure during the contact formation process, has inferior contact resistance to unalloyed metal silicide, that is, a metal silicide without any metal germanide mixed within. An example of an agglomeration triggered increase in the sheet resistance of the alloy of silicide and germanide was reported in Pey et al., “Thermal Reaction of nickel and Si0.75Ge0.25 alloy,” J. Vac. Sci. Technol. A 20(6), November/December 2002, pp. 1903-1910, after an anneal above 700° C. in the alloy of nickel and Si0.75Ge0.25.
It has also been discovered during the course of research leading to the present invention that selective epitaxial growth of Si:C alloy produces a very rough surface with multiple facets. Metal silicides formed upon such surfaces have degraded performance compared to normal silicide formed on flat surface containing no carbon. Whatever the mechanism for this degradation may be, the selective Si:C epitaxial growth process currently available in the industry produces Si:C alloy surfaces which produces inferior silicide with higher contact resistance compared to a flat silicon surface containing no carbon.
Furthermore, it has been discovered that not only the reaction rate of the Si:C selective epitaxy process is very slow, but there is also a limit on the thickness of the Si:C films that can be grown by selective epitaxy process currently available in the industry. Apparently, the incorporation of carbon into silicon changes some of the reaction mechanism of conventional silicon epitaxy causing the thickness of the epitaxially grown Si:C film saturates in time. This means that the increase in the height of the source and the drain through the use of Si:C selective epitaxy has a limit, and that Si:C selective epitaxy is not conducive to manufacturing of NFET structures with highly raised source and drain relative to the height of the gate dielectric.
Therefore, there exists a need for a semiconductor structure and methods that produce stable and low contact resistance on SiGe alloy surfaces.
There exists another need for a semiconductor structure and methods that produce stable and low contact resistance on Si:C alloy surfaces.
Also, there exists a need for a semiconductor structure and methods that produce a thick epitaxial silicon alloy, especially a thick epitaxial Si:C alloy, above the level of the gate dielectric.
Finally, there exists a need for a semiconductor structure and methods that provide stable low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate.